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SOC Verification using SystemVerilog

SOC Verification using SystemVerilog

FREE

SOC Verification using SystemVerilog

A comprehensive course that teaches System on Chip design verification concepts and coding in SystemVerilog Language

Details

This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in SystemVerilog language - which is the most popular Hardware Description Language used for SOC design and verification in semiconductor industry. The course is organised into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate and verify using a free browser based Simulator and Waveform viewer. Quizzes are also added to test the students knowledge and progress.

Part 2 of the course covering advanced and industry standard verification methodologies like OVM//UVM will follow based on feedback on this course

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Video Quality
Support
Cost

Lectures:
35
Students:
9918
level:
All
Language:
English
Institute:
Udemy

FREE